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Modern loaded-board assemblies are multi-layer constructions, heavily populated by under-the-package bonded devices such as microBGAs, Column -Grid Arrays, Flip-Chip Arrays, etc. Such boards offer very limited physical access for traditional bed-of-nail testers and other test issues arise, such as defects associated with buried components, higher operating frequencies placing more emphasis on signal integrity, lower power supply voltages, need for more-accurate thermal analysis, electromagnetic compatibility, and so on. As a result, many systems companies are struggling to understand how to design new boards to support prototype board debug (design verification and defect analysis), volume production manufacturing test (defect detection and location), systems integration (backplane test), and field service (fast fault finding and fix). One solution is to develop ad-hoc Design For Testability (DFT) methodologies carrying back the board testing problem to the earliest phase of the board development. This implies the development of new DFT techniques, new skills, new competence centers, new methodologies, and new organizations. BTW targets these problems and provides a forum to discuss possible solutions.